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library ieee;

use ieee.std_logic_1164.all;

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entity AND_ent is

port(   x: in std_logic;

        y: in std_logic;

        F: out std_logic

);

end AND_ent;  

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architecture behav1 of AND_ent is

begin

    process(x, y)

    begin

        -- compare to truth table

        if ((x='1') and (y='1')) then

            F <= '1';

        else

            F <= '0';

        end if;

    end process;

end behav1;

architecture behav2 of AND_ent is

begin

    F <= x and y;

end behav2;

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LIBRARY ieee ;

 USE ieee.std_logic_1164.all;

 USE ieee.std_logic_signed.all;

 ENTITY adder4arithm IS

   PORT ( Cin   : IN   STD_LOGIC;

              X, Y  : IN   STD_LOGIC_VECTOR(3 DOWNTO 0);

          S     : OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);

          Cout  : OUT  STD_LOGIC );

 END adder4arithm;

 ARCHITECTURE Behavior OF adder4arithm IS

    SIGNAL Sum: STD_LOGIC_VECTOR(4 DOWNTO 0);

 BEGIN

    Sum  <= ('0' & X)+ Y + Cin;

    S    <= Sum(3 DOWNTO 0);

    Cout <= Sum(4);

 END Behavior;